1. Field of the Invention
The present invention relates generally to the field of semiconductor technology. More particularly, the present invention relates to a method for fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device with reduced Miller capacitance.
2. Description of the Prior Art
As known in the art, the rise of on-resistance of traditional planar power DMOS devices (DMOS) is contributed from the channel region, the accumulation layer and junction field effect transistor (JFET). In order to reduce the resistance of the above-mentioned area, trench type power devices (UMOS) are proposed. Since JFET region does not exist in a UMOS, the cell size can be reduced and the channel density is increased, thereby resulting in a lower on-resistance, but on the other hand, the UMOS devices has higher gate-to-drain capacitance (Miller capacitance) that affects the switching speed.
Therefore, one purpose of the present invention is to reduce the Miller capacitance of the power devices by incorporating a recess structure and by using an oxidation process to fill the recess. For the tight pitched structure, the oxidation process may have larger process window than the conventional deposition process. The disclosure can also be used in the fabrication process of a trench type transistor with superjunction structure and is capable of overcoming the difficulty of filling the high aspect ratio trenches.